Wire bonding is a common, cost-effective and flexible interconnect technology for making interconnections between the bond pads of an earlier successfully probed integrated circuit (IC) die and its packaging (leads of its leadframe) during semiconductor device assembly. The IC die is generally placed onto a lead frame, wire bonded to connect the bond pads of the IC die to leads of the lead frame, and the IC and the leadframes is then encapsulated in a plastic molding material.
The reliability of a wirebonded packaged IC device during performance of its function in its application is dependent on the quality of the wirebond interconnections. The quality of a wirebond is determined by the strength of the interfaces between the bondwires and the bond pads, as well as between the bondwires and the lead fingers.
Bondwires can comprise aluminum, copper, silver, or gold. Copper bondwires are comparatively low in cost as compared to gold bondwires, and have the ability of being used at smaller diameters providing the same performance as gold. However, copper bondwires significantly increase the risk for bondwire-related time zero defects and future bondwire-related continuity induced failures.
Bondwire integrity testing can be electrically-based or non-electrically-based. Non-electrically-based bondwire integrity testing methods includes bond pull testing, ball-bond shear testing, and visual inspection. However, once the molding is completed, non-electrically-based bondwire integrity testing other than X-ray imaging are no longer possible. X-ray imaging allows a visual inspection of wirebonds of the package. However, a problem with X-rays is that the image is not always clear, and the manual process of inspecting X-ray images is generally slow and imprecise.
In a known electrical bondwire integrity testing method, almost every pin of a packaged IC device can be checked by using a conventional Electrostatic Discharge (ESD) cell that has a diode characteristic when tested while referenced to ground. Older IC devices without ESD cells have a parasitic diode referenced to ground. A small amount of current is provided ‘backwards’ to a VSS pin from signal pins being bondwire integrity tested. The current is used to forward bias the diode coupled between the signal pin and the VSS pin. The current passes through the respective bondwires and bondwire interfaces to the bond pads (ball and stitch bonds on the bond pads), with the resulting voltage drop being the current multiplied by bondwire and interface resistances, will be present on the signal pin as a voltage.
Electrically-based bondwire integrity methods also include contact resistance (CRES) testing which also depends on the parasitic diode forward conduction paths. CRES testing also needs two separate read points to determine the CRES. CRES testing uses fixed limits set using a full package test bondwire integrity process distribution (over many package test lots) which results in wide CRES test limits, thus rendering the CRES method a generally insensitive bondwire integrity test method.